[LLVMdev] Doubt related to scheduling with shift operation

[Sachin.Punyani at microchip.com]

Hi,

 

For the case, please see the ".ll" file attached. Here I am doing a
right shift on 32 bits by constant amount (specifically by 8).  

 

My target is an 8-bit target. Therefore while performing a shift (right
or left) on long (32 bits) it is legalized in 4 smaller units. After
performing the shift, this value should be stored at the same location.
So order of the stores does matter. But all 4 stores are parallel in the
code and do not have any control flow dependency between them. Therefore
these stores are scheduled in some order not correct for the result. 

 

Please provide some input on this. Also how does the scheduler determine
the order when 16-bit quantity is shifted (in the same example) because
the DAG for 16 bit shift is similar with both the stores in parallel.

I have tried shift operation for 64 bits on some 32 bit targets also.
The DAG looks similar with stores in parallel. How does the scheduler
determine the order in such cases?

 

This is not a target specific doubt. But pic16 is the only target that
creates that such a scenario. For 8-bit target command line used:- 

 

llc -march=pic16 try.bc

 

Regards

Sachin

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