[LLVMdev] Possible bug in ExpandShiftWithUnknownAmountBit

[Javier Martinez]

Hi Duncan,

The problem is the implementation of the expansion. Perhaps an example 
can help illustrate better. Take the case of a 64-bit integer shifted 
left by say 6 bits and is decomposed using 32-bit registers. Because 6 
is less than the 32 (the register size) the resulting low part should be 
equal to the source low part shifted left by 6 bits. The current 
implementation places a zero instead. All other values have similar 
errors. Below is the current and proposed expansion in pseudo C++ for 
all shift functions. Please let me know if I something is unclear.

- SHL:
[Current]
dst.lo = (shift < regsize) ? 0 : src.lo << shift;
dst.hi = (shift < regsize) ? src.lo << shift : ((src.hi << shift) | 
(src.lo >> regsize - shift));

[Proposed]
dst.lo = (shift < regsize) ? src.lo << shift : 0;
dst.hi = (shift < regsize) ? ((src.hi << shift) | (src.lo >> shift - 
regsize)) : src.lo << shift - regsize;

- SRL/SRA
[Current]
dst.lo = (shift < regsize) ? src.hi >> shift : ((src.lo >> shift) | 
(src.hi << regsize - shift));
dst.hi = (shift < regsize) ? 0 : src.hi >> shift;

[Proposed]
dst.lo = (shift < regsize) ? ((src.lo >> shift) | (src.hi << regsize - 
shift)) : src.hi << shift - regsize;
dst.hi = (shift < regsize) ? src.hi << shift : 0;

Thanks,
Javier

On 12/1/2009 1:01 AM, Duncan Sands wrote:
> Hi,
>
>> I'm working in adding support for 64-bit integers to my target. I'm 
>> using
>> LLVM to decompose the 64-bit integer operations by using 32-bit 
>> registers
>> wherever possible and emulating support where not. When looking at 
>> the bit
>> shift decomposition I saw what seems to be a bug in the 
>> implementation. The
>> affected function is ExpandShiftWithUnknownAmountBit in
>> LegalizeIntegerTypes.cpp. Below is the original code and the proposed 
>> fix.
>> Could someone please review the changes? If they are correct how do I go
>> about submitting a patch?
>
> can you please describe the problem and how you fix it (in words, not 
> code).
>
> Thanks,
>
> Duncan.