[LLVMdev] Problems with DAG Combiner

[Jakob Stoklund Olesen]

On 24/08/2009, at 01.19, Stripf, Timo wrote:
>
> I had also a lot of problems to get the i1 operations working. E.g.  
> I had to override the getSetCCResultType to get is working and for  
> ADDE/ADDC the i1 target registers are hardcoded.

What is your SetCCResultType now?

Can you compile the CodeGen/Blackfin/basic-i1.ll test case? I never  
got that one working with legal i1. The IA64 back-end couldn't compile  
it either.

> I'm writing the back-end to research the influence of several ISA  
> characteristics on the processor performance. Large parts of my back- 
> end are automatically generated by a general description. So I'm  
> very interested in keeping the DAG as realistic as possible.

I hate to scope-creep your research, but I would be very interested in  
an analysis of native i1 operations versus promotions. Are you  
planning an ISA version with built-in i1 AND/OR/XOR?

>> I don't think you have to write custom lowering code to get the
>> behaviour you want. Have you tried this:
>>
>>   setOperationAction(ISD::OR, MVT::i1, Promote);
>
> I tried Promote and Expand but on the 2.5 code base it is not  
> implemented.

Yeah, you definitely need 2.6. Blackfin has  
setOperationAction(ISD::OR, MVT::i16, Promote), and it took a few bug  
fixes to get that working.

/jakob