[LLVMdev] Problems with DAG Combiner
Jakob Stoklund Olesen
stoklund at 2pi.dk
Sun Aug 23 10:12:40 PDT 2009
On 23/08/2009, at 18.42, Stripf, Timo wrote:
> Hi all,
>
> i’m writing an back-end for a new research processor architecture
> and have problems with the DAG Combiner. The processor architecture
> supports i1 and i32 registers. 1-bit registers are mainly used as
> comparison result but basic operations like OR are not possible
> between i1 registers. So I wrote custom lowering for i1 OR
> operations and replaced it by (trunc (or (aext x), (aext y))). Now
> the problem is that the DAG Combiner optimizes it back to an i1 OR
> operations that is not supported by the architecture.
The IA64 target has just been removed from the tree. It was the only
target with legal i1 values, so there could be some problems.
The Blackfin DSP can do simple i1 operations with the CC flag and
status bits. Initially I also marked i1 as a legal type, but it caused
a lot of problems. Now I pretend that the CC register can hold an i32.
It just happens to always hold the values 0 and 1. The i1 logical
operations are rarely needed, and they can be custom inserted when
necessary, see BlackfinTargetLowering::LowerADDE().
I don't think you have to write custom lowering code to get the
behaviour you want. Have you tried this:
setOperationAction(ISD::OR, MVT::i1, Promote);
If you can get your target to work with a legal i1 type, it would be
great. The Blackfin target could use that as well.
> What is the best way to solve this problem? I take a look at the
> DAG Optimizer and for this OR operation it calls
> DAGCombiner::SimplifyBinOpWithSameOpcodeHands that folds (OP (aext
> x), (aext y)) -> (aext (OP x, y)). No check if the new operation is
> legal is performed.
When LegalOperations is set, the DAG combiner must not create illegal
operations. It is a bug if it does. I recently fixed this in the first
if statement in SimplifyBinOpWithSameOpcodeHands(). Perhaps you could
add a check to the second if statement and submit a patch?
/jakob
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