[LLVMdev] What is the state of LLVM's ARM backend

[Xerxes Rånby]

Den 2009-04-08 14:44, Xerxes Rånby skrev:
> Hello Evan and Robert
> I have been investigating the unexpected test failures from the ARM
> nightly builders in order to get a better picture why the ARM backend
> don't pass the whole testsuite: I have run the failing tests manually on
> my arm board and can now categorize most of the thirteen unexpected
> CodeGen failures in four categories:
>
> 1. llvm don't lower MVT::i64 properly on arm errors
> http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/i64armLoweringRelatedErrors/
> example:
>
> root at overo:/home/xerxes/llvm-test/fail/CodeGen/notnativelysupported# llvm-as<  2008-02-04-ExtractSubvector.ll  | llc
> llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/include/llvm/Target/TargetLowering.h:158: llvm::TargetRegisterClass* llvm::TargetLowering::getRegClassFor(llvm::MVT) const: Assertion `RC&&  "This value type is not natively supported!"' failed.
> Stack dump:
> 0.	Program arguments: llc
> 1.	Running pass 'ARM Instruction Selection' on function '@main'
> Aborted
>
>    

Three of these i64 related test passes after applying the attached patch 
from pr 3898 !
http://llvm.org/bugs/show_bug.cgi?id=3898

Thanks Jakob!

Could someone commit this one to the svn tree?

[xranby at pusspuss llvm]$ llvm-as < 
test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll | llc -march=arm
     .file    "<stdin>"


     .text
     .globl    main
     .align    2
main:
     mov r3, #0
.LBB1_1:    @ bb15
     b .LBB1_1    @ bb15
     .size main, .-main

[xranby at pusspuss llvm]$ llvm-as < 
test/CodeGen/X86/dagcombine-buildvector.ll | llc -march=arm
     .file    "<stdin>"


     .text
     .globl    test
     .align    2
test:
     ldr r1, [sp, #+12]
     str r1, [r0, #+12]
     ldr r1, [sp, #+8]
     str r1, [r0, #+8]
     stmia r0, {r2, r3}
     bx lr
     .size test, .-test

[xranby at pusspuss llvm]$ llvm-as < test/CodeGen/Generic/select-cc.ll | 
llc -march=arm
     .file    "<stdin>"


     .text
     .globl    vector_select
     .align    2
vector_select:
     stmfd sp!, {r4, r5, r6, r7, lr}
     mov r4, r3
     mov r5, r2
     mov r6, r1
     mov r7, r0
     mov r2, #0
     mov r3, #0
     bl __gedf2
     ldr r2, [sp, #+32]
     cmp r0, #0
     mov r3, r4
     movge r3, r2
     ldr r1, [sp, #+28]
     cmp r0, #0
     mov r2, r5
     movge r2, r1
     ldr r12, [sp, #+24]
     cmp r0, #0
     mov r1, r6
     movge r1, r12
     ldr r12, [sp, #+20]
     cmp r0, #0
     mov r0, r7
     movge r0, r12
     ldmfd sp!, {r4, r5, r6, r7, pc}
     .size vector_select, .-vector_select

[xranby at pusspuss llvm]$



/*                               The failing i64 related tests are now 
only two left:                            */

(wrongcodegen)
llvm-as < test/CodeGen/Generic/asm-large-immediate.ll | llc -march=arm | 
grep 68719476738

and
(shifttolower)
llvm-as < test/CodeGen/X86/vshift_split.ll | llc -march=arm
llc: ARMISelLowering.cpp:1426: llvm::SDValue ExpandSRx(llvm::SDNode*, 
llvm::SelectionDAG&, const llvm::ARMSubtarget*): Assertion 
`N->getValueType(0) == MVT::i64 && (N->getOpcode() == ISD::SRL || 
N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"' failed.
0   llc 0x089afeb8
Stack dump:
0.    Program arguments: llc -march=arm
1.    Running pass 'ARM Instruction Selection' on function '@update'
Avbruten (SIGABRT)
[xranby at pusspuss llvm]$

> 2. lowering sometimes produces unexpected results error
> http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/loweringproducesunexpectedresults/
> example:
>
> root at overo:/home/xerxes/llvm-test/fail/CodeGen/loweringproducesunexpected# llvm-as<  multiple-return-values-cross-block-with-invoke.ll | llc
> llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1579: llvm::SDValue<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDValue): Assertion `(Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1&&  Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == MVT::Flag))&&  "Lowering call/formal_arguments produced unexpected # results!"' failed.
> Stack dump:
> 0.	Program arguments: llc
> 1.	Running pass 'ARM Instruction Selection' on function '@foo'
> Aborted
>
>    

This have been fixed by applying the patch made by Sandeep
http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-April/021754.html

Could someone commit this one to the svn tree?

> 3. Could not match memory address errors
> http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/matchmemoryaddress_inlineasmfailure/
> example:
>
> root at overo:/home/xerxes/llvm-test/fail/CodeGen/matchmemoryaddress# llvm-as<  2007-04-08-MultipleFrameIndices.ll | llc
> Could not match memory address.  Inline asm failure!
> 	.file	"<stdin>"
> Aborted
>
>    
This one still needs a fix... :/

> 4. softfloat related errors
> http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/
> example:
>
> root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as<  2007-11-19-VectorSplitting.ll  | llc
> SoftenFloatResult #0: 0x614e00: f32 = undef
> llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0&&  "Do not know how to soften the result of this operator!"' failed.
> Stack dump:
> 0.	Program arguments: llc
> 1.	Running pass 'ARM Instruction Selection' on function '@execute_shader'
> Aborted
>
>    
This one are fixed and comitted to the svn tree!
Thanks Duncan

Cheers and have a great day!
Xerxes