[LLVMdev] Using CallingConvLower in ARM target (ARM i64 lowering fixed by applying patch from pr 3898 )

[Xerxes Rånby]

Den 2009-04-16 13:37, Xerxes Rånby skrev:
> Some failing tests have now gotten better error reporting than before:
>
> $ llvm-as<  test/CodeGen/Generic/select-cc.ll | llc
> Formal argument #0 has unhandled type i64
> Stack dump:
> 0.    Program arguments: llc
> 1.    Running pass 'ARM Instruction Selection' on function '@vector_select'
> Aborted
>
> $ llvm-as<  test/CodeGen/X86/dagcombine-buildvector.ll | llc
> Formal argument #1 has unhandled type i64
> Stack dump:
> 0.    Program arguments: llc
> 1.    Running pass 'ARM Instruction Selection' on function '@test'
> Aborted
>    

These two test succeeds after applying the attached patch from pr 3898
http://llvm.org/bugs/show_bug.cgi?id=3898

[xranby at pusspuss llvm]$ llvm-as < test/CodeGen/Generic/select-cc.ll | 
llc -march=arm
     .file    "<stdin>"


     .text
     .globl    vector_select
     .align    2
vector_select:
     stmfd sp!, {r4, r5, r6, r7, lr}
     mov r4, r3
     mov r5, r2
     mov r6, r1
     mov r7, r0
     mov r2, #0
     mov r3, #0
     bl __gedf2
     ldr r2, [sp, #+32]
     cmp r0, #0
     mov r3, r4
     movge r3, r2
     ldr r1, [sp, #+28]
     cmp r0, #0
     mov r2, r5
     movge r2, r1
     ldr r12, [sp, #+24]
     cmp r0, #0
     mov r1, r6
     movge r1, r12
     ldr r12, [sp, #+20]
     cmp r0, #0
     mov r0, r7
     movge r0, r12
     ldmfd sp!, {r4, r5, r6, r7, pc}
     .size vector_select, .-vector_select

[xranby at pusspuss llvm]$ llvm-as < 
test/CodeGen/X86/dagcombine-buildvector.ll | llc -march=arm
     .file    "<stdin>"


     .text
     .globl    test
     .align    2
test:
     ldr r1, [sp, #+12]
     str r1, [r0, #+12]
     ldr r1, [sp, #+8]
     str r1, [r0, #+8]
     stmia r0, {r2, r3}
     bx lr
     .size test, .-test

[xranby at pusspuss llvm]$


Thanks Jakob!

Cheers, and have a great day!
Xerxes