[LLVMdev] confused about llvm.memory.barrier

[Duncan Sands]

> In its usual configuration, an x86 family CPU implements a strong memory
> ordering constraint for all loads and stores, so as long as the ordering
> of the read and write operations is preserved no atomic operation is
> required between them. XCHG and CAS only become necessary when you are
> coordinating reads and writes across processors. MFENCE similarly.

So... gcc's memory barriers are of no use on a multi-processor system?
These are pretty common nowadays, so that sounds very bad...

Ciao,

Duncan.