[LLVMdev] A question about instruction operands.

[sanjiv gupta]

I have a question:
In the pattern below from X86

def INC8r  : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
			"inc{b}\tdst",
		  [(set GR8:$dst, (add GR8:$src, 1))]>;

Since we are emitting only "inc $dst",
What makes sure that the $src and $dst are same register?

- Sanjiv