[LLVMdev] TableGen Calling Convention help

[Villmow, Micah]

With my backend code gen I want to assign calling parameters to a list
of registers, but since I'm targeting a virtual instruction set. I don't
want to be limited by the number of registers. Is there a way using
TableGen to specify just a starting register to assign to for the
CallingConv class and then have it just use sequential registers?

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

4555 Great America Pkwy,

Santa Clara, CA. 95054

P: 408-572-6219

F: 408-572-6596

 

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080915/8a513cb1/attachment.html>