[LLVMdev] Instruction MVT::ValueTypes

[Dan Gohman]

On Sep 3, 2008, at 1:14 PM, David Greene wrote:

> On Tuesday 02 September 2008 16:47, Evan Cheng wrote:
>> On Sep 2, 2008, at 10:42 AM, David Greene wrote:
>>> Is there an easy way to get the MVT::ValueType of a  
>>> MachineInstruction
>>> MachineOperand?  For example, the register operand of an x86 MOVAPD
>>> should
>>> have an MVT::ValueType of v2f64.  A MOVAPS register operand should
>>> have an
>>> MVT::ValueType of v4f32.
>>
>> The short answer is no. A op of a number of different VTs can map to
>> the same instruction.
>
> In general, that may be true, but for most instructions isn't it  
> 1:1?  What
> are some examples where it isn't 1:1?  The vector processor needs to
> know how the data in the register is organized to compute the  
> operation, after
> all.
>
> Thinking about MOVAPS / MOVAPD I suppose one could argue that it's
> perfectly legal to do a MOVAPD on a vector register that contains 8- 
> bit data.
> It's just bits, after all, but there is a "preference" to what  
> should be in
> the register for performance reasons.  It's not good to mix-and- 
> match MOVAPD
> and MOVAPS on the same data.

For the case of MOVAPS vs. MOVAPD vs. MOVDQU (assuming you have a
micro-architecture where there's actually a difference), this can be
achieved by having instruction selection select the right instructions.
For example, find code like this in X86InstrSSE.td:

def : Pat<(alignedloadv2i64 addr:$src),
           (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
def : Pat<(loadv2i64 addr:$src),
           (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;

and change it to not select MOVAPS for that microarchitecture, for
example.

Dan