[LLVMdev] Targeting a platform with virtual instruction set and unlimited virtual registers

[Sanjay Soman]

I am working on a LLVM backend for a new platform. The target has a virtual instruction set and unlimited virtual registers. After going through LLVM documentation and source code, it looks like there are two possible ways to implement it with LLVM:
1) Method #1: follow common code generator path (TableGen, LLVMTargetMachine, etc), similarly as the Sparc and x86 targets. Since the target has unlimited number of virtual registers, register allocation is no use here. I can skip the register allocation by overloading the register allocator with one does no allocation. Is there any assumption in this infrastructure that would prevent from doing so?
2) Method #2: follow the custom code generator path, similar as the CBackend and MSIL targets.
 
I’d like to evaluate which method is more appropriate for this particular target. Method#1 provides some optimizations at machine instruction level (in this case, the virtual instruction set). Is the custom path capable of doing the same?
 
Thanks,
-Sanjay


      
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