[LLVMdev] sign extensions on loads?

[Evan Cheng]

On Oct 6, 2008, at 1:40 PM, Villmow, Micah wrote:

> I have a simple test case that my code generator handles fine when  
> using optimizations, but when I disable optimizations, It turns into  
> a sequence of instructions that I can’t figure out what to setup to  
> get it to generate the correct code.
> The instructions in question are:
> %tmp1 = load float* %test               ; <float> [#uses=1]
>  %conv = fpext float %tmp1 to double             ; <double> [#uses=1]
>
> Which emits the following dag:
> f64,ch = load 01809908, 018092A8, 01809110 <0035A544:0> <anyext f32>  
> alignment=4

This is probably created by dag combiner. You should tell it that's  
illegal:

setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);

Evan

>
> If the load and the fpext were emitted seperatly, I could handle  
> them with my fpext and load patterns in tablegen. However, since  
> they are being combined into a single DAG, I have not been able to  
> figure out how to get them to generate the correct code. I can match  
> against the load and generate a store instruction, but I need to  
> emit a conversion instruction instead based on the src and dst data  
> types.  Any idea where I would pattern this without having to custom  
> lower the load instruction?
> Here is my current pattern:
>
> def generic_load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
>     return isGenericLoad(dyn_cast<LoadSDNode>(N));
> }]>;
> def ADDRf : ComplexPattern<i32, 2, "SelectADDRf", [frameindex], []>;
> // Load Memory Operations
> multiclass LOADm<string asm, PatFrag OpNode, ComplexPattern addr> {
>     def _i32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
>         asm, [(set (i32 GPR:$dst), (OpNode addr:$ptr))]>;
>     def _f32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
>         asm, [(set (f32 GPR:$dst), (OpNode addr:$ptr))]>;
>     def _i64 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
>         asm, [(set (i64 GPR:$dst), (OpNode addr:$ptr))]>;
>     def _f64 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
>         asm, [(set (f64 GPR:$dst), (OpNode addr:$ptr))]>;
> }
> defm GENERICLOAD : LOADm<"mov $dst, $ptr", generic_load, ADDRf>;
>
> This pattern matches the load, but it doesn’t handle the conversion.  
> Any idea on how?
>
> Thanks for your time,
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
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