[LLVMdev] Multi-instruction patterns, tablegen and chains

[Dan Gohman]

Hi Matthijs,

On Nov 3, 2008, at 9:05 AM, Matthijs Kooijman wrote:
>
> Am I doing something wrong here, or is tblgen mistaken?

I think you're doing something that is beyond what tblgen is
currently prepared for. But it's interesting :-).

Having rd and RD have explicit chain operands and results
sounds like the right thing to do. This is needed to prevent
them from being reordered or CSE'd.

Having tblgen pretend that the MOVE isn't the root seems a bit
counter-intuitive though.

I think it would be useful to have a way to explicitly tell
tblgen which node(s) in the output pattern to hook up the chain(s)
to. I believe this is related to a problem David Greene is seeing,
where he has a case involving multiple chains.
A fully general approach would be to make chain operands explicit
in patterns, and to invent some syntax for identifying chain
results. It might look something like this:

def : Pat<(rd ch:$input_chain, imm:$addr)[$output_chain],
           (MOVE (RD ch:$input_chain, imm:$addr)[$output_chain])>;

This would be a pretty big change though.

An alternative that's a bit less ambitious would be to have
tablegen search the output pattern for nodes which are declared
to support chain operands/results, and if it finds exactly one
such node, use that node to hook up all the chain
operands/results. If it finds more than one, it could issue
an error. This would probably be simpler and less invasive,
and probably enough for your specific example, though it
wouldn't be as general-purpose.

Dan