[LLVMdev] Whole-function isel

[Christopher Lamb]

I know that this has been discussed (at least in passing) a few times  
on the list, but I couldn't locate a bug for it. Have any  
architectural plans been made for it?

Are there architectural roadblocks with the current LLVM  
infrastructure that will complicate the process? What has demotivated  
the implementation of this so far (is it not that big a benefit on  
important targets, too much time/effort for the payoff)?

In toying with some code generators I've been frustrated in getting  
the code gen prepare pass + isel to implement the heuristics I need  
to match some addressing modes and I believe that whole-function isel  
might be the answer.
--
Christopher Lamb



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