[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.

[Dan Gohman]

The new SUBREG target-independent instructions aren't getting
mayLoad/mayStore flags set correctly.

For example, in the generated X86GenInstrInfo.inc file,
there is only one entry for INSERT_SUBREG:

   { 5,  4,      1,      0,      "INSERT_SUBREG", 0, 0, NULL, NULL,  
OperandInfo107 },  // Inst #5 = INSERT_SUBREG

THe sixth field is zero, which means it doesn't have the the
MayLoad flag set.

x86-64 does have a few variants of INSERT_SUBREG, and one of
them does have a load:

def : Pat<(i64 (anyext (loadi32 addr:$src))),
           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
                                                     x86_subreg_32bit)>;

This isn't currently being reflected in the InstrInfo tables.
Naively, it seems like we should add a separate INSERT_SUBREGrm
instruction, and so on, or something like that, in order to be able
to have accurate InstrInfo tables. Does anyone familiar with the
new subregs infastructure have an opinion on this?

Dan