[LLVMdev] Backend for the ZPU - a stack based / zero operand CPU

[Evan Cheng]

On Jun 22, 2008, at 11:16 AM, Øyvind Harboe wrote:

> On Fri, 20 Jun 2008, [ISO-8859-1] ?yvind Harboe wrote:
>>> The ZPU has two instructions that I'd also like to use. These  
>>> instructions
>>> can push a value from deeper down on the stack and also pop a value
>>> from the stack and store them deeper down on the stack.
>>
>> Sounds like the Intel X87 floating point stack, which we support.
>
> GCC does as well. Supporting floating point is a different game
> than "normal" instructions since it interferes with frame pointers,  
> etc.

We mean ZPU looks like x86 fp stack. We handle it by register  
allocating it like a normal register based cpu than add a x87  
stackifer pass to convert it to stack operations.
>
>
>>
>>> The ZPU needs relaxation. Immediate values and
>>> pc/sp relative references have variable lengths.
>>>
>>> Does llvm support ?nstruction relaxation?
>>
>> Yes, many targets (e.g. arm, mips, ppc) have branch offset  
>> restrictions.
>
> I wrote the relaxation support in gas + the GCC linker. Do I need to
> reimplement it somehow?

You do not have to. Take a look at PPC and ARM branch fix up passes.  
llvm backends compute exact length of instructions so it can determine  
when it is necessary to convert a conditional branch to a conditional  
branch of the opposite condition and a unconditional branch.

Evan

>
>
> Basically the ZPU's assembler instruction supports 32 bit offsets
> and it is the linker chooses another assembler instruction w/smaller
> offset.
>
>> LLVM doesn't provide an assembler, you should use GAS.
>
> Do I have to use GAS + the GCC linker?
>
> Does llvm offer an alternative? (Just curious).
>
> -- 
> Øyvind Harboe
> http://www.zylin.com/zy1000.html
> ARM7 ARM9 XScale Cortex
> JTAG debugger and flash programmer
>
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