[LLVMdev] Regarding ARM CodeGen

Evan Cheng evan.cheng at apple.com
Mon Jul 14 15:10:06 PDT 2008


On Jul 14, 2008, at 12:59 PM, kapil anand wrote:

> Hi all,
>
> I am using LLVM compiler and CodeGen  for generating ARM binaries.
>
> I was going through the code for ARM backend. I noticed that the ARM  
> Condition field( Bits 31-28) is generated by converting the  
> conditions used in icmp and branch. For example, if I have following  
> C Code
>
> int a,b,c,d;
> c = a+b;
>
> if(c==0)
>      d = a + 10;
>
>
> Then I get ( Assembly Instructions with opcodes only)
>
> add
> cmp
> addeq
>
>
> ( basically converting branch to the predicate condition field)
>
> I have a few questions regarding the above operation.
> 1. If I use GCC on above code, then I get following .s output:
>    adds
>    addeq
>
> I don't  get the intermediate compare instruction, which I got when  
> I used LLVM. So, does LLVM ARM Backend assume that only "cmp" and  
> "test" instructions can set the Status flags and not the usual  
> arithmetic instructions. Is there any way of specifying to Backend  
> that add can also modify status flag through "s" bit.

Right. X86 backend has the same issue. It's not taking advantage of  
the fact that instructions can set the condition register bits. It's a  
known codegen deficiency. On x86 it's generally not a *huge* issue but  
I have no idea what its impact is on various ARM implementations.

>
>
> 2. Also, when I looked at ISelLowering file, I noticed that  
> conditions used in "icmp" instructions are converted to ARM  
> Predicate Condition fields. Icmp has only "10" conditions, which map  
> to corresponding "10" conditions in ARM Condition field but ARM can  
> have fourteen conditions. If we consider the mapping shown in  
> ISelLowering File, then following four conditions are left:
> "VS": Overflow Set
> "VC" : Overflow Clear
> "MI" : Minus
> "PL": Plus
>
> So, does this mean that it is not possible to obtain the above  
> conditions are predicate if we use LLVM Compiler framework.

It's not clear to me how those are modeled in the llvm level.

Evan

>
>
> Thanks
>
> Regards,
> Kapil Anand
>
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080714/fa12ae42/attachment.html>


More information about the llvm-dev mailing list