[LLVMdev] Quad precision registers

[Fernando Magno Quintao Pereira]

Hi, guys.

     I was browsing through SparcRegisterInfo.td, and I did not find 
support for quad-precision floating-point registers, that is, a single 
register of 128 bits aliasing four registers of 32. As this is predicted 
in the Sparc V8 manual (http://www.sparc.org/standards/V8.pdf, page 33), 
do you guys plan on adding this feature?

all the best,

Fernando