[LLVMdev] variable arguement intrinsics

[aditya vishnubhotla]

hi

I want to use two intrinsic functions which should be
placeholders 
for some instructions which should not be executed by
the backend.

So these two intrinsics should just keep the data
dependencies while i
 try to 
separate set of instructions(with more of data flow)
to be executed on 
hardware.

One intrinsic which takes care of the data
dependencies  required for
 proper 
execution of the hardware set and the second intrinsic
which takes care
 of 
the data dependencies of other instructions on this
hardware set.

My question is can we create intrinsics with variable
number of
 arguments? if 
so, how?

My other question is can we use the data type "void"
to represent the
 datatype 
of the arguments instead of creating multiple
intrinsic for each
 possible 
type of the dependencies?

thank you
aditya

P.S:


> 
> On Jan 9, 2008, at 2:12 AM, aditya vishnubhotla
> wrote:
> 
> >
> > Hi,
> >
> > I am writing a pass which identifies the
> parts(basic
> > blocks/functions) of
> > the input algorithm with more of data flow or
> control
> > flow. These parts are to
> > be separated executed by different backends.
> > My idea is to insert replacement basic blocks with
> > intrinsic instructions
> > within the basic block. These instructions should
> > satisfy the data
> > dependencies within the LLVM data structure and
> should
> > do the parameter
> > marshalling for switching to the other
> architecture to
> > and fro.
> >
> > Dependencies of the different passes:
> >
> >  analysis part
> >          |
> >        filter
> >      /      \
> > ppc          custom backend
> 
> Ok.
> 
> >
> > Switching between the ppc and custom backend would
> be
> > by using different
> > filter passes in two compiler runs.
> >
> > I have a couple of questions regarding the problem
> > outlined above:
> > Is the approach using intrinsic instructions
> > worthwile?
> 
> Probably. If what you are trying to represent is
> truly target  
> specific then using intrinsics is good solution.
> 
> > What has to be done to the existing backends to
> make
> > these new instrinsic
> > instructions known?
> 
> You need to add Intrinsics??.td file to include/llvm
> as well as  
> instruction selection patterns / code to translate
> them to target  
> specific instructions.
> 
> > Is there an way to eliminate two compiler runs,
> one
> > for each backend?
> 
> Right now, the only way I see that can be possible
> is if you have a  
> single target capable of handling codegen for both
> parts. So for  
> example, if you can make the target into a variant
> of ppc, then you  
> can potentially dynamically switch between the two
> for different  
> BB's. But I would suggest you put the idea away for
> now. It would  
> seem to me the problem you described present plenty
> of challenges for  
> now. :-)
> 
> Evan
> 
> >
> > Best regards
> > Aditya
> >
> >
> >        
> >
> 



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