[LLVMdev] compare and swap

[Andrew Lenharth]

I was working on compare and swap and ran into the following problem.
Several architectures implement this with a load locked, store
conditional sequence.  This is good, for those archs I can write
generic code to legalize a compare and swap (and most other atomic
ops) to load locked store conditional sequences (then the arch only
had to give the instr for ldl, stc to support all atomic ops (this
applies to mips, arm, ppc, and alpha)).  However, I have to split the
basic block at the CAS instruction and create two more basic blocks.

This isn't currently possible during legalize, nor during the initial
SelectionDAG formation  (the tricks switch lowering uses only work for
terminator instructions).

Anyone have an idea?  The patch as it stands is attached below.  X86
is a pseudo instruction because the necessary ones and prefixes aren't
in the code gen yet, but I would imagine they will be (so ignore that
ugliness).  The true ugliness can be seen in the alpha impl which open
codes it, including a couple relative branches.  The code sequence for
alpha is identical to ppc, mips, and arm, so it would be nice to lower
these to the correct sequences before code gen rather than splitting
(or hiding as I did here) basic blocks after code gen.

Andrew
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