[LLVMdev] [Mesa3d-dev] Folding vector instructions

[Zack Rusin]

On Tuesday 30 December 2008 15:30:35 Chris Lattner wrote:
> On Dec 30, 2008, at 6:39 AM, Corbin Simpson wrote:
> >> However, the special instrucions cannot directly be mapped to LLVM
> >> IR, like
> >> "min", the conversion involves in 'extract' the vector, create
> >> less-than-compare, create 'select' instruction, and create 'insert-
> >> element'
> >> instruction.
>
> Using scalar operations obviously works, but will probably produce
> very inefficient code.  One positive thing is that all target-specific
> operations of supported vector ISAs (Altivec and SSE[1-4] currently)
> are exposed either through LLVM IR ops or through target-specific
> builtins/intrinsics.  This means that you can get access to all the
> crazy SSE instructions, but it means that your codegen would have to
> handle this target-specific code generation.

I think Alex was referring here to a AOS layout which is completely not ready. 
The currently supported one is SOA layout which eliminates scalar operations.

> The direction we're going is to expose more and more vector operations
> in LLVM IR.  For example, compares and select are currently being
> worked on, so you can do a comparison of two vectors which returns a
> vector of bools, and use that as the compare value of a select
> instruction (selecting between two vectors).  This would allow
> implementing min and a variety of other operations and is easier for
> the codegen to reassemble into a first-class min operation etc.
>
> I don't know what the status of this is, I think it is partially
> implemented but may not be complete yet.

Ah, that's good to know!

> >> I don't have experience of the new vector instructions in LLVM, and
> >> perhaps
> >> that's why it makes me feel it's complicated to fold the swizzle and
> >> writemask.
>
> We have really good support for swizzling operations already with the
> shuffle_vector instruction.  I'm not sure about writemask.

With SOA they're rarely used (essentially never unless we "kill" a pixel") [4 
x <4 x float> ] {{xxxx, yyyy, zzzz, wwww}, {xxxx, yyyy, zzzz, www}...} so with 
SOA both shuffles and writemask come down to a simple selection of the element 
within the array (whether that will be good or bad is yet to be seen based on 
the code in gpu llvm backends that we'll have)
 
> Sure, it would be very reasonable to make these target-specific
> builtins when targeting a GPU, the same way we have target-specific
> builtins for SSE.

Actually currently the plan is to have essentially a "two pass" LLVM IR. I 
wanted the first one to never lower any of the GPU instructions so we'd have 
intrinsics or maybe even just function calls like gallium.lit, gallium.dot, 
gallium.noise and such. Then gallium should query the driver to figure out 
which instructions the GPU supports and runs our custom llvm lowering pass 
that decomposes those into things the GPU supports. Essentially I'd like to 
make as many complicated things in gallium as possible to make the GPU llvm 
backends in drivers as simple as possible and this would help us make the 
pattern matching in the generator /a lot/ easier (matching gallium.lit vs 9+ 
instructions it would be be decomposed to) and give us a more generic GPU 
independent layer above. But that hasn't been done yet, I hope to be able to 
write that code while working on the OpenCL implementation for Gallium.

z