[LLVMdev] Shifts that use only 5 LSBs.

[Daniel M Gessel]

I'm working on a Target that only uses the 5 lsbs of the shift amount.

I only have 32 bit registers, no 64 bit, so 64 bit math is emulated,  
LLVM doing the transformations whenever I can get it to.

I think I'm seeing a case where it ultimately looks like a standard  
multiword shift (from e.g. Hacker's Delight) is being inline expanded  
that assumes at least 6 bits of the shift is paid attention to (i.e.  
it looks like it assumes x >> 32 == 0 if x is 32 bits, but for me x >>  
32 == x).

(A) What does LLVM assume about "shift width"?
(B) Is there a way I can tell it that I've only got 5 bits?

Thanks,

Dan