[LLVMdev] Implementing llvm.memory.barrier on PowerPC

[Dale Johannesen]

OK, I've checked it in for you, thanks.   Please do contact Chris  
about write access.

On Aug 22, 2008, at 12:38 AMPDT, Gary Benson wrote:

> No, I don't.
>
> Cheers,
> Gary
>
> Dale Johannesen wrote:
>> This looks OK to check in, do you have write access?
>>
>> On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote:
>>
>>> Dale Johannesen wrote:
>>>> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
>>>>> I'm trying to implement llvm.memory.barrier on PowerPC.  I've
>>>>> modelled my patch (attached) on the implementation in X86, but
>>>>> when I try and compile my test file (also attached) with llc I
>>>>> get the error "Cannot yet select: 0x10fa4ad0: ch = MemBarrier
>>>>> 0x10fa4828, 0x10fa4c68, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0,
>>>>> 0x10fa4be0".  This presumably means my "membarrier" pattern
>>>>> isn't being found... but why?
>>>>
>>>> Because the i1's in the .bc file get promoted to i32 on ppc,
>>>> instead of i8.  I've forgotten why this is, there's a setting
>>>> somewhere.  If you change the i8's in membarrier to i32's it
>>>> works.
>>>
>>> Thanks for that.  Attached is a working implementation of
>>> llvm.memory.barrier.
>>>
>>>> Thanks for doing this btw.
>>>
>>> No problem, I need it! ;)
>>>
>>> Cheers,
>>> Gary
>>>
>>> -- 
>>> http://gbenson.net/
>
>> Index: include/llvm/IntrinsicsPowerPC.td
>> ===================================================================
>> --- include/llvm/IntrinsicsPowerPC.td	(revision 54985)
>> +++ include/llvm/IntrinsicsPowerPC.td	(working copy)
>> @@ -26,6 +26,9 @@
>>   def int_ppc_dcbtst: Intrinsic<[llvm_void_ty, llvm_ptr_ty],  
>> [IntrWriteMem]>;
>>   def int_ppc_dcbz  : Intrinsic<[llvm_void_ty, llvm_ptr_ty],  
>> [IntrWriteMem]>;
>>   def int_ppc_dcbzl : Intrinsic<[llvm_void_ty, llvm_ptr_ty],  
>> [IntrWriteMem]>;
>> +
>> +  // sync instruction
>> +  def int_ppc_sync : Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
>> }
>>
>>
>> Index: lib/Target/PowerPC/PPCInstrInfo.td
>> ===================================================================
>> --- lib/Target/PowerPC/PPCInstrInfo.td	(revision 54985)
>> +++ lib/Target/PowerPC/PPCInstrInfo.td	(working copy)
>> @@ -773,6 +773,10 @@
>>                      [(store F8RC:$frS, xaddr:$dst)]>;
>> }
>>
>> +let isBarrier = 1 in
>> +def SYNC : XForm_24_sync<31, 598, (outs), (ins),
>> +                        "sync", LdStSync,
>> +                        [(int_ppc_sync)]>;
>>
>> // 
>> = 
>> = 
>> = 
>> ----------------------------------------------------------------------= 
>> ==//
>> // PPC32 Arithmetic Instructions.
>> @@ -1357,5 +1361,13 @@
>> def : Pat<(extloadf32 xaddr:$src),
>>           (FMRSD (LFSX xaddr:$src))>;
>>
>> +// Memory barriers
>> +def : Pat<(membarrier (i32 imm:$ll),
>> +                      (i32 imm:$ls),
>> +                      (i32 imm:$sl),
>> +                      (i32 imm:$ss),
>> +                      (i32 imm:$device)),
>> +           (SYNC)>;
>> +
>> include "PPCInstrAltivec.td"
>> include "PPCInstr64Bit.td"
>> Index: lib/Target/PowerPC/PPCISelLowering.cpp
>> ===================================================================
>> --- lib/Target/PowerPC/PPCISelLowering.cpp	(revision 54985)
>> +++ lib/Target/PowerPC/PPCISelLowering.cpp	(working copy)
>> @@ -78,9 +78,6 @@
>>   // from FP_ROUND:  that rounds to nearest, this rounds to zero.
>>   setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
>>
>> -  // PowerPC has no intrinsics for these particular operations
>> -  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
>> -
>>   // PowerPC has no SREM/UREM instructions
>>   setOperationAction(ISD::SREM, MVT::i32, Expand);
>>   setOperationAction(ISD::UREM, MVT::i32, Expand);
>> Index: lib/Target/PowerPC/PPCInstrFormats.td
>> ===================================================================
>> --- lib/Target/PowerPC/PPCInstrFormats.td	(revision 54985)
>> +++ lib/Target/PowerPC/PPCInstrFormats.td	(working copy)
>> @@ -309,6 +309,17 @@
>>   let Inst{31}    = 0;
>> }
>>
>> +class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
>> +               string asmstr, InstrItinClass itin, list<dag>  
>> pattern>
>> +  : I<opcode, OOL, IOL, asmstr, itin> {
>> +  let Pattern = pattern;
>> +  let Inst{6-10}  = 0;
>> +  let Inst{11-15} = 0;
>> +  let Inst{16-20} = 0;
>> +  let Inst{21-30} = xo;
>> +  let Inst{31}    = 0;
>> +}
>> +
>> class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,  
>> string asmstr,
>>                InstrItinClass itin, list<dag> pattern>
>>   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
>
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>
> -- 
> http://gbenson.net/
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