[LLVMdev] Alias analysis and instruction level parallelism

[Pertti Kellomäki]

Devang Patel wrote:
> If you handle this at LLVM IR level then you've access to all the  
> alias info and GEP instructions are directly available to you.  LLVM  
> IR supports vector types for SIMD style parallelism and target  
> specific code generators lowers them appropriately.

Our target is a statically scheduled VLIW style processor,
which may have custom FUs designed by the user. This means
that the instruction scheduler needs to have very detailed
knowledge of the available FUs, latencies, the interconnection
network etc.  The main problem is not exploiting some set of
vector style FUs, but rather packing parallel operations
into wide instructions. We would love to do this at the level
of LLVM IR, but it does not seem to be possible.
-- 
Pertti