[LLVMdev] Lowering operations to 8-bit!

[Alireza.Moshtaghi at microchip.com]

Attached please find the gdb backtrace dump and the postscript file of
the DAG right before assertion.
The red Node is the current Node in LegalizeOp()
The only thing that I am customizing before we get here is the
FORMAL_ARGUMENTS. At this time I don't really care about the arguments,
just want to get some global values working. When I trace the program,
it is well passed the legalizing of formal arguments when it crashes so
I'm not sure if I may be breaking something in there.
Here is my code in the formalizing arguments (copied ISD::MERGE_VALUES
from PowerPC implementation, not sure if it is really needed)


static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG){
  SmallVector<SDOperand, 8> ArgValues;
  SDOperand Root = Op.getOperand(0);
  // Return the new list of results.
  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
                                    Op.Val->value_end());
  const Function* Fn = DAG.getMachineFunction().getFunction();
  std::cout<<Op.Val->getNumValues();
  std::cout<<"----------------- "<<__FUNCTION__<<" handling
FORMAL_ARGUMENTS of"<<Fn->getName()<<std::endl;std::cout.flush();
  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e;
++ArgNo) {
    
    MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
    
    switch (ObjectVT){
    default: assert(0 && "Unhandled argument type!");
    case MVT::i32: cout<<"------------ i32"<<std::endl;break;
    case MVT::i64: cout<<"------------ i64"<<std::endl;break;
    case MVT::f32: cout<<"------------ f32"<<std::endl;break;
    case MVT::f64: cout<<"------------ f64"<<std::endl;break;
    case MVT::v4f32: cout<<"------------ v4f32"<<std::endl;break;
    case MVT::v4i32: cout<<"------------ v4i32"<<std::endl;break;
    case MVT::v8i16: cout<<"------------ v8i16"<<std::endl;break;
    case MVT::v16i8: cout<<"------------ v16i8"<<std::endl;break;
      break;
    } //end switch
  } //end for
  
  ArgValues.push_back(Root);
  return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0],
ArgValues.size());
}

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Chris Lattner
Sent: Friday, September 28, 2007 12:04 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Lowering operations to 8-bit!


On Sep 28, 2007, at 11:36 AM, <Alireza.Moshtaghi at microchip.com>  
<Alireza.Moshtaghi at microchip.com> wrote:

> I moved my code to 2.1 but still the same.
> If I make ADD i16 legal, then it goes through, but it has problem
> expanding it to i8.
> Should I go ahead and customize it and do the same for all  
> instructions?
> Or there is a more general thing that I can do?

I really can't tell without more information.  How is it failing?   
Can you add a stack trace and pdf of the dump of the dag being  
legalized when it crashes?

-Chris
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