[LLVMdev] Lowering operations to 8-bit!

[Alireza.Moshtaghi at microchip.com]

I moved my code to 2.1 but still the same.
If I make ADD i16 legal, then it goes through, but it has problem
expanding it to i8.
Should I go ahead and customize it and do the same for all instructions?
Or there is a more general thing that I can do?

A.

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Chris Lattner
Sent: Thursday, September 27, 2007 8:27 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Lowering operations to 8-bit!


On Sep 27, 2007, at 4:35 PM, <Alireza.Moshtaghi at microchip.com>  
<Alireza.Moshtaghi at microchip.com> wrote:

> I'm working on version 2.0
> The assertion at line 2380 of LegalizeDAG.cpp fails when it is  
> trying to
> lower the add with i16.
>
> assertion reads:
> assert(MVT::isVector(Node->getValueType(0)) &&
>   "Cannot expand this binary operation!");
>
> I am trying to compile a very simple program as follows:
>
> short var;
> void foo(void)
> {
> 	Var++;
> }
>
> The input bytecode, (in addition to the debug stuff) contains:
>
> 	%tmp  = load i16* @var        ;<i16> [#uses=1]
> 	%tmp1 = add  i16  %tmp, 1     ;<i16> [#uses=1]
> 	store  i16 %tmp1, i16* @var
> 	br  label %return
> return:         ;preds = %entry
>
> Is the above giving any clue, or you need more info?

I'd suggest trying mainline or LLVM 2.1.  In 2.1 (but not 2.0) it is  
possible to implement 128-bit addition on a 32-bit cpu.  This seems  
similar to your situation.

-Chris 
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