[LLVMdev] Q about instruction pattern matching

[Evan Cheng]

On Sep 24, 2007, at 1:12 AM, Andreas Fredriksson wrote:

> On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote:
>
>> I am going to suggest something shocking. :) Since you will end up  
>> writing a
>> bunch of target specific code anyway, you might a well write a target
>> specific pass that change generic instructions into data register  
>> variant
>> ones when necessary.
>
> Hi Evan,
> wouldn't this generate fairly terrible code if each address register
> use has to be preceded by instructions to make an address register
> hold the right value?

No. I would suggest doing this as a instruction selection post pass.  
It would operate on DAGs so you still get the benefit of SDNode CSE,  
etc. Scheduling and register allocation happen later.

Let me clarify. Write "generic" instructions, i.e. those that use /  
def DR32, with patterns. So right after isel, all the DAG nodes will  
be of the dx variant, e.g. ADD_32_dx_dx. Also write AR instruction  
variants such as ADDA_32_dx. These do not have patterns so they  
aren't used during selection. Add a post pass to replace load / store  
operands by replacing them with identical nodes except for the  
"correct" opcodes.

I think this mechanism will work. There is probably a cleaner  
solution. But I am not seeing it right now.

Evan


>
> I'm a bit confused here, wouldn't this run after the register
> allocator, or is there a way to have the register allocator run after
> I've gone through and "target-legalized" all instructions?
>
> Thanks,
> // A
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