[LLVMdev] Q about instruction pattern matching

[Andreas Fredriksson]

On 9/21/07, Christopher Lamb <christopher.lamb at gmail.com> wrote:

> ISel patterns are matched against DAGs before register allocation. So you
> are correct that ISel patterns can't take into account register classes. The
> register classes in the patterns are a selection constraint for the register
> allocator if that instruction is chosen, not a constraint on choosing that
> pattern.
>
> Here's a possible way to proceed for now:
> Define ADDA_32_dx without a pattern. Then in C++ pattern code for matching
> address operands select add operations on addresses to ADDA_32_dx. This way
> you know that the add your selecting is going to be used as an address and
> you can safely tell the register allocator to put the value in an address
> register.

Thanks, I guess that makes sense. I might as well go ahead and create
a general-purpose register class but then require that some operations
only target the data registers. For instance, multiplication is going
to require data registers while indirect addressing requires address
registers.

Could something like the Uses and Defs constraints apply to whole
register classes as well? For instance, I assume the register
allocated is going to guarantee that EAX:EDX is not allocated around
an x86 integer division, and that the inputs end up in the right
registers. If those constraints "ripple up" through the function,
couldn't that be augmented to solve this problem as well so that
arithmetic would automatically select the data registers?

Thanks,
// A