[LLVMdev] Q about instruction pattern matching

[Andreas Fredriksson]

Hi,
I'm trying to describe the patterns for the m68k instructions ADD and
ADDA when used with a data register operand for the source. Basically,
ADD operates on anything but address registers and immediates, and
ADDA works on address registers only so I'm going to need both
instructions in my instruction set.

These are the two problematic definitions; by themselves they produce
the intented effect. AR is the address register class, DR32 is the
data register class (no overlap):

// 32-bit add DR->DR
def ADD_32_dx_dx : I<(outs DR32:$dst), (ins DR32:$src1, DR32:$src2),
"add.l $src2, $dst", [(set DR32:$dst, (add DR32:$src2, DR32:$src1))]>;

// 32-bit add DR->AR
def ADDA_32_dx : I<(outs AR:$dst), (ins AR:$src1, DR32:$src2), "adda.l
$src2, $dst", [(set AR:$dst, (add AR:$src1, DR32:$src2))]>;

Tablegen tells me that "Pattern '(add:i32 DR32:i32:$src2,
DR32:i32:$src1)' is impossible to select", but I can't figure out why.
Are register classes not taken into account in the pattern matching or
am I doing something else wrong?

Thanks,
Andreas