[LLVMdev] Adding address registers to back-end

[Evan Cheng]

On Oct 21, 2007, at 10:17 AM, Boris Boesler wrote:

> Hi!
>
>>>  I'm writing a new back-end for a new architecture. First, I'll do
>>> some "tests" with an existing back-end (I chose the Sparc back-end).
>>> My architecture has special address-registers and I want to add such
>>> new address-registers to my Sparc back-end.
>>> ....
>>>  The GlobalAddress for variable c is replaced by an ADD(HI(c), LO
>>> (c)) during lowering. I assume the code-generator cant place values
>>> in the address registers? All address-registers are elements in the
>>> register sets IntRegs and AddrRegs.
>>
>> /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
>> multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
>> ....
>> }
>>
>> defm ADD   : F3_12<"add", 0b000000, add>;
>>
>> Instruction ADD output register class is IntRegs. It does not match
>> AddrRegs. That's why you are getting the assertion.
>
>  The address register set AddrRegs is a subset of IntRegs. Do you
> compare the register set identifiers instead of the register itself
> and if it is within a set?

>
>  So, what should I do next? What do you suggest? Modify the register
> allocator?

This assertion is in ScheduleDAG.cpp. It's asserting while lowering  
the DAG into a sequence of machine instructions. Right now, it's  
pretty simple minded, excepting the register class of the virtual  
register to *exactly* match the register class of the instruction use  
operand definition. Changing the code to allow the case you've  
described, i.e. the definition RC is a subset of the use RC, sounds  
like a good approach. Patch is welcome.

Evan

>
>
> Thanks,
> Boris
>
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