[LLVMdev] Examples of aliased register banks

[Dale Johannesen]

On Oct 10, 2007, at 10:34 AM, Fernando Magno Quintao Pereira wrote:

>
> Dear guys,
>
>      I hope you don't mind if my question is a little off topic,  
> but I have
> been using LLVM to do register allocation for the x86 aliased register
> bank, and now I want to find more applications for my algorithm. So, I
> wish I could find an example of a computer architecture with more  
> than two
> level of aliasing in the register bank. For instance, SPARC has 16
> floating point registers that can be further divided into 32 single
> precision registers. Is there an example of an architecture that  
> allows
> registers to be divided into two, four or more smaller registers? I
> thought at first in MMX, but the MMX instructions do not let me access
> each subregister independently.

The PowerPC condition code register is addressed as 32 bits, 8 4-bit
fields, or 32 1-bit fields by different instructions.  Currently llvm  
models
only the last two.