[LLVMdev] alias information on machine instructions

[Chris Lattner]

On Mon, 30 Apr 2007, Florian Brandner wrote:
> i`m working on a machine instruction scheduler for an VLIW architecture.
> loads are somewhat expensive on this architecture, thus i would like to
> reorder unrelated loads/stores to better hide load latencies.
>
> to do this, i would need alias information on machine instructions,
> i.e., which machine instructions may access the same memory region.
>
> as far as i know, this is not available at the moment? are there any
> plans to get aliasing information on machine instructions?

There are a couple of ways to do this.  Is your scheduler a prepass 
scheduler (before regalloc) or a post-pass scheduler (after regalloc)?  If 
you want to extract maximal parallelism, I assume you want a prepass 
scheduler.  In that case, you should look into the SelectionDAG based 
schedulers, which do have alias information on them.

-Chris

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