[LLVMdev] Instruction Scheduling in LLVM

[Evan Cheng]

Some isel nodes produce MVT::Flag value because it has to scheduled  
right before its use (one use per flag value). An example of this is  
a compare and a conditional branch (only because we do not model  
condition code as a register right now).

The scheduler is honoring the request by treating a chain of flagged  
nodes as a single scheduling unit.

Evan

On May 1, 2007, at 6:19 PM, Kaushik Kumar wrote:

> Hello,
>
> I am working with the SelectionDAG/ScheduleDAG framework to  
> implement a variation of the List scheduling Algorithm in LLVM.
> I was trying to understand the existing List scheduler  
> implementation in LLVM. I have a doubt about the SUnits structure  
> which contain flagged nodes together. The instructions within a  
> Sunit are scheduled as a single unit. My understanding is that the  
> nodes in the original DAG fall into exactly one of the Sunits. So,  
> I was wondering if the instructions (SDNodes) within a SUnit need  
> to be scheduled seperately? For example, it may be necessary to  
> insert a No-op between the instructions (within one SUnit) in  
> certain cases. Or is the nodes which are flagged together (apart  
> from the main node) are psuedo ops which don't need to be actually  
> emitted?
> A general overview will also be helpful.
> (The documentation does not provide much details and the source is  
> too complicated to understand at times).
>
> Thank you
> -Kaushik
>
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