[LLVMdev] PR1350 (Vreg subregs) questions

[Christopher Lamb]

What's the best way to get an SDNode through to DAG scheduling  
without getting mangled during Lowering/ISel?

When should subregs be flattened to actual registers: AsmPrinter?  
Somewhere in LiveIntervals, during RegAlloc?

Is there are common API used to turn vregs into physregs that could  
be changed to flatten any subregs in a central location?
--
Christopher Lamb