[LLVMdev] Register based vector insert/extract

[Christopher Lamb]

That'd be great.

On Jun 6, 2007, at 3:16 PM, Nate Begeman wrote:

> Hi Christopher,
>
> I can send you what I have for that so far, that works pretty well.
>
> Nate
>
> On Jun 6, 2007, at 3:06 PM, Christopher Lamb wrote:
>
>>
>> On Apr 24, 2007, at 12:01 PM, Chris Lattner wrote:
>>
>>> Yes, we need those.  I think these are the major pieces needed.   
>>> These are
>>> all relatively small and independent pieces, so we can tackle  
>>> these one at
>>> a time.
>>
>> <snip>
>>
>>> 4. The DAG scheduler pass (which creates machine instrs from dag  
>>> nodes)
>>>     currently thinks of register operands as simple unsigned's  
>>> for vreg
>>>     #'s.  This needs to be extended to be vreg+subreg pairs (see
>>>     'CreateVirtualRegisters').
>>> 5. We need to decide how to represent subregs in the DAG.  Your
>>>     SDSubOperand idea is fine, but I don't think it needs to be  
>>> an actual
>>>     new subclass of SDOperand.  Instead, it could just be a  
>>> binary SDNode,
>>>     where the LHS is the register input and the RHS is a  
>>> TargetConstant
>>>     specifying the subreg#.
>>> 6. [optional] We would like syntax to create these things for  
>>> writting
>>>     patterns in the .td file instead of requiring custom matching  
>>> code.
>>> 7. The register allocator needs to rewrite subreg references using
>>>     #1.  This should be very simple.
>>
>>
>> For 5 I am currently creating new binary SDNodes for 'from_subreg'  
>> and 'to_subreg' in ISD, is this in line with your thinking for the  
>> design Chris? The issue I ran into is that you essentially need  
>> subreg insert and extract.
>>
>> --
>> Christopher Lamb
>>
>>
>>
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--
Christopher Lamb



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