[LLVMdev] Pattern matching questions

[Chris Lattner]

On Thu, 11 Jan 2007, Evan Cheng wrote:
>>
>> It doesn't. Here's the pattern:
>>
>> let isTerminator = 1, isBarrier = 1, noResults = 1 in {
>>   let isReturn = 1 in {
>>     def RET: BRForm<0b00010101100, (ops),
>>                         "bi $$lr",
>>                         BranchResolv,
>>                         [(retflag)]>;
>>   }
>> }
>>
>> Output from make:
>>
>> llvm[0]: Building SPU.td code emitter with tblgen
>> tblgen: /work/scottm/llvm/utils/TableGen/CodeGenInstruction.h:118:
>> std::pair<unsigned int, unsigned int>
>> llvm::CodeGenInstruction::getSubOperandNumber(unsigned int) const:
>> Assertion `i < OperandList.size() && "Invalid flat operand #"' failed.
>> make: ***

This is clearly a bug in tblgen.

> Please file a bug with a reduced test case for it.

I attempted to add $$lr to other instruction patterns in existing targets, 
but couldn't reproduce it.  Evan is right, we need a bug report or some 
way to reproduce it.

My guess is that you haven't specified all bits for the encoding of the 
RET instruction.  If you disable generation of the code emitter for your 
target (i.e. remove SPUGenCodeEmitter.inc from your makefile) it should 
work around this.

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/