[LLVMdev] bitconvert for multi-typed RegisterClasses

[Evan Cheng]

On Feb 13, 2007, at 11:09 PM, Christopher Lamb wrote:

>>>
>>> Also, I was incorrect in thinking that the bitconvert patterns I
>>> mentioned in the original post had solved my problems. I ended up
>>> having to explicitly add patterns for the f32 types to the
>>> InstrInfo.td. And then, it only seems to work if I add a pseudo
>>> instruction with the following selection pattern (store (f32 Regs:
>>> $src), ADDRri:$addr), rather than adding a pattern such as the
>>> following:
>>>
>>> def : Pat<(store (f32 Regs:$src), ADDRri:$addr), (ST32 Regs:$src,
>>> ADDRri:$addr)>;
>>
>> I can't tell from the information you have provided. How is ST32
>> defined?
>
> def ST32	: F0<opcode,
> 				(ops MEMri:$addr, Regs:$src),
> 				"st32 [$addr], $src",
> 				[(store Regs:$src, ADDRri:$addr)]>;
>

Seems to me the pattern should be:

def : Pat<(store (f32 Regs:$src), ADDRri:$addr), (ST32 ADDRi:$addr,  
Regs:$src)>;

You have the order of operands reversed?

Evan