[LLVMdev] Linux/ppc backend

[Nicolas Geoffray]

Hi Chris,

Chris Lattner wrote:
>> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. 
>> However, Linux and Darwin do not have the same set
>> of non-callee saved registers. I don't know how to make the if(isDarwin) test 
>> in here
>>     
>
> Take a look at ARM/ARMRegisterInfo.td for an example of this
I tried to define Defs just like ARMRegisterInfo.td does with different 
subtargets, but i get the obvious
message:
Value 'Defs' of type 'list<Register>' is incompatible with initializer '[{
(the code is at the end of this mail)


I'm not sure how to play with Defs and what to write in a .td file. I 
tried a top-level if with a Predicate:
def IsMacho   : Predicate<"Subtarget->isMachoABI()">;
if (isMacho) let Defs = ....
else Defs = ...

But this fails too.

Any other ideas on how to get this right?

Thx,
Nicolas



let isCall = 1, noResults = 1, PPC970_Unit = 7,
  // All calls clobber the non-callee saved registers...
  Defs = [{
 
 
  static const unsigned Defs_ELF[] = 
{R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
          F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
          
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
          LR,CTR,
          CR0,CR1,CR5,CR6,CR7}
 
  static const unsigned Defs_Macho[] = 
{R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
          F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
          
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
          LR,CTR,
          CR0,CR1,CR5,CR6,CR7}
 
  GPRClass::iterator
    GPRClass::allocation_order_begin(const MachineFunction &MF) const {
      const TargetMachine &TM = MF.getTarget();
      const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>();
      if (Subtarget.isMachoABI()){
        return Defs_Macho;
      } else {
        return Defs_ELF;
      }
    }

    GPRClass::iterator
    GPRClass::allocation_order_end(const MachineFunction &MF) const {
      const TargetMachine &TM = MF.getTarget();
      const MRegisterInfo *RI = TM.getRegisterInfo();
      const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>();
      GPRClass::iterator I;
      if (Subtarget.isMachoABI()) {
        I = Defs_Macho + (sizeof(Defs_Macho)/sizeof(unsigned));
      } else {
        I = Defs_ELF + (sizeof(Defs_ELF)/sizeof(unsigned));
      }

      return I;
    }
  }]

  in {
  // Convenient aliases for call instructions
  def BL  : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
                            "bl $func", BrB, []>;  // See Pat patterns 
below.
  def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
                            "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
  def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), 
"bctrl", BrB,
                           [(PPCbctrl)]>;
}