[LLVMdev] bitconvert for multi-typed RegisterClasses

[Evan Cheng]

>
> Thanks Evan,
>
> I had tried something like this, but ran into some problems.
>
> llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1478: failed assertion
> `MVT::isVector(VT) && "Cannot promote this load!"'
>
> and
>
> llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1766: failed assertion
> `MVT::isVector(VT) && "Unknown legal promote case!"'
>
>
> it appears that for load/store only vector types of equivalent bit-
> widths can be promoted in this way, but one cannot promote an f32 to
> an i32.

Right. I am afraid will have to add separate patterns for f32 cases.

>
> Also, I was incorrect in thinking that the bitconvert patterns I
> mentioned in the original post had solved my problems. I ended up
> having to explicitly add patterns for the f32 types to the
> InstrInfo.td. And then, it only seems to work if I add a pseudo
> instruction with the following selection pattern (store (f32 Regs:
> $src), ADDRri:$addr), rather than adding a pattern such as the
> following:
>
> def : Pat<(store (f32 Regs:$src), ADDRri:$addr), (ST32 Regs:$src,
> ADDRri:$addr)>;
>
> The above pattern produced the following error because the
> TargetOperandInfo for the 1 operand of the store had a NULL register
> class.
>
> llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:304: failed assertion
> `RC && "Don't have operand info for this instruction!"'
>
> Why the pseudo-op doesn't have this problem, I'm not clear.

I can't tell from the information you have provided. How is ST32  
defined?

Evan
>
> Thanks
> --
> Christopher Lamb
>
>>
>>>
>>> Thanks
>>> --
>>> Christopher Lamb
>>>
>>>
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