[LLVMdev] variant generation question

[Scott Michel]

I've got an instruction that has the following pattern (R32C is the  
32-bit register class):

(set R32C:$rT, (or (and R32C:$rA, R32C:$rC),
                    (and R32C:$rB, (not R32C:$rC))))

tblgen generates the following variants (I've dropped the R32C for  
brevity):

(or (and $rA, $rC), (and $rB, (not $rC)))  # original
(or (and $rA, $rC), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rA, $rC))
(or (and (not $rC), $rB), (and $rA, $rC))

I would have expected four additional patterns, each with the (and  
$rC, $rA) variant in it. But I only get the above four.

Is this a bug or a feature? :-)


-scooter
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070209/419244f2/attachment.html>