[LLVMdev] Custom GEP lowering

[Scott Michel]

On Aug 28, 2007, at 7:12 PM, Christopher Lamb wrote:

>
> On Aug 28, 2007, at 6:15 PM, Scott Michel wrote:
>
>> On Aug 28, 2007, at 7:02 AM, Dan Gohman wrote:
>>
>>> On Mon, Aug 27, 2007 at 07:26:55PM -0700, Scott Michel wrote:
>>>> It looks like I need to be able to intercept GEP lowering (in
>>>> SelectionDAGLowering::visitGetElementPtr) and insert something else
>>>> other than the shifts and adds. The basic problem is that CellSPU
>>>> loads and stores on 16-byte boundaries. Consequently, the SPU  
>>>> backend
>>>> has to do the load or store differently than most normal
>>>> architectures that have byte-addressable operations.
>>>
>>> In TOT, load and store instructions have an alignment attribute
>>> which is
>>> useful for addressing similar needs on other architectures. For
>>> example,
>>> this attribute is used on x86, which also has a bunch of  
>>> instructions
>>> which require 16-byte alignment. x86 uses it quite late, after
>>> legalize,
>>> and I don't know if that's appropriate for the CellSPU target, but
>>> wherever you're doing the lowering, could you use the load and store
>>> alignment attribute?
>>
>> I'm aware of this attribute, but it doesn't help. The underlying
>> problem is that CellSPU does not know how to natively perform byte-
>> level addressing. For example, here's an indexed stack instruction to
>> load register $3:
>>
>> 	ldq	$3, 4($sp)
>>
>> In reality, the "4($sp)" doesn't mean what you think it means in the
>> PPC and x86 worlds: that's 4 x 16 -- load quadword (ldq) appends four
>> zero bits to the right of the offset. To get at the 4th byte requires
>> loading from 0($sp) and some vector shuffling. (Dan: Think about
>> older Cray hardware... you'll immediately understand!)
>
> Isn't this just an ISel issue? You have to ISel unaligned load/ 
> store's to more complex code is all. It seems very simple to  
> current targets that support indexed and non-indexed addressing  
> modes. In this case it's simply that you have to implement the un- 
> indexed modes in terms of a more complex expression based on an  
> indexed load.
>
> I tackled a similar issue in Ageia's back end in just this way.

Will do a little debugging and investigating and get back to you on  
this... although I suspect the answer is still going to be custom  
lowering GEPs. I'd like to be wrong!


-scooter
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