[LLVMdev] Atomic memory barrier DAG representation

[Chandler Carruth]

Hello,

I am in the process of implementing the atomic operations and
synchronization constructs in LLVM. The memory synchronization construct
is described at http://llvm.org/docs/LangRef.html#int_memory_barrier and
has the following problem:

There are 15 variations on the memory barrier to handle the various
ordering constraints desired. Most architectures however only have
support for a few of these variations, and the rest are conservatively
lowered to an all out barrier. I would like to represent this as
concisely in the SelectionDAG as possible to make pattern matching it in
the targets clear and simple.

I propose the following, based on some initial feedback from Chris and
others:

- Represent a memory barrier as a single SDNode, with a constant operand
representing which precise memory barrier variant needs to be implemented.
- Pattern match off of the barrier SDNode and specific values of the
operand for specialized instructions on supporting architectures
- Pattern match all other operands to use a conservative fallback
instruction.

Does this sound reasonable to those more well versed in CodeGen? My
apologies if this doesn't entirely make sense, I am still new to the
codegen side of LLVM, and learning my way around.

Thanks,
-Chandler