[LLVMdev] Register based vector insert/extract

[Christopher Lamb]

On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote:

> On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote:
>
>> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote:
>>
>>> On Mon, 23 Apr 2007, Christopher Lamb wrote:
>>>> How can one let the back end know how to insert and extract  
>>>> elements of
>>>> a vector through sub-register copies? I'm at a loss how to do  
>>>> this...
>>>
>>> You probably want to custom lower the insertelement/extractelement
>>> operations for the cases you support.  Take a look at
>>> X86TargetLowering::LowerEXTRACT_VECTOR_ELT for some examples of  
>>> how to do
>>> this.
>>
>> The issue I'm having is that there is no extract/insert  
>> instruction in the ISA, it's simply based on using subregister  
>> operands in subsequent/preliminary instructions. At the pointer of  
>> custom lowering register allocation has not yet been done, so I  
>> don't have a way to communicate the dependency.
>>
>
> An example is in order:
>
> If I have a register v4r0 with subregisters {r0, r1, r2, r3} and a  
> DAG that looks like
>
> load v4si <- extract_element 2 <- add -> load i32
>
> I'd like to be able to generate
>
> load v4r0
> load r10
> add r11, r10, r2 <== subregister 2 of v4r0

I see that Evan has added getSubRegisters()/getSuperRegisters() to  
MRegisterInfo. This is what's needed in order to implement the  
register allocation constraint, but there's no way yet to pass the  
constraint through the operands from the DAG. There would need to be  
some way to specify that the SDOperand is referencing a subvalue of  
the produced value (perhaps a subclass of SDOperand?). This would  
allow the register allocator to try to use the sub/super register  
sets to perform the instert/extract.

Is any of this kind of work planned? The addition of those  
MRegisterInfo functions has me curious...

--
Christopher Lamb