[LLVMdev] best way to implement complex addressing modes

[Chris Lattner]

On Wed, 6 Sep 2006, [UTF-8] Rafael Esp?ndola wrote:
> The ARM has some very powerful and complex addressing modes. For
> example, the  data processing instructions (and, orr, add, ..) have an
> addressing mode that has 11 options (imm, reg, and 9 reg + some
> shift).
>
> I am considering 3 ways to implement this:
>
> 1) define one instruction that has an ARM specific addressing mode
> that covers all 11 possibilities.
> 2) define 11 instructions.
> 3) a mix of the two
>
> I believe that implementation 1 would be the most elegant one. It
> would have a one to one correspondence with the ARM Architecture
> Reference Model.
>
> For two to work it would be necessary to write custom select code to
> use the more uncommon addressing options.
>
> For three I could use the multiclass feature to implement add_ri and
> add_rr. The add_ri instruction would use a custom addressing mode for
> the second operand.
>
> Currently I am planning to implement 3 because it looks like to be the
> easiest to implement.

I'm not sure exactly what the constraints you have are, but I'd suggest 
using a 'complexpattern' to match these, along with some custom C++ code 
to do the actual matching.  This mechanism works well for real addressing 
modes, but can also work for generic other things as well.  If you have 
specific questions, please ask.  Also, don't be afraid to experiment and 
try different approaches, sometimes the best way to appreciate a good 
solution is to learn what's terrible about the bad ones :)

-Chris

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