[LLVMdev] Implicit defs

[Chris Lattner]

On Sat, 14 Oct 2006, Roman Levenstein wrote:
> Is it possible to dynamically define implicit defs for some
> instructions?

Yes!  This is what explicit operands are :).  Specifically, if you want to 
vary on a per-opcode basis what registers are used/def'd by the 
instruction, you can just add those registers as explicit use/def operands 
in the machine instruction with the physical registers directly filled in.

> The reason for this wish is that some of the calling conventions on my
> target use different sets of physical registers for their return
> values. Therefore I cannot describe it by one static set of regs, as
> shown above.

Right.

> One obvious solution is to define several machine instructions for a
> CALL, each defining its own set of implicitly defined registers. But it
> is not very elegent in my opinion. Are there any other ways to achieve
> the same result? May be it can be solved simpler?

This is another solution which works great if there are only a few 
variants.

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/