[LLVMdev] matching "ret 0"

[Chris Lattner]

On Tue, 16 May 2006, [UTF-8] Rafael Esp?ndola wrote:
> Or any tips for debugging instruction selection?

The most important thing that you can do, is to set up graphviz on your 
system, to allow you to visualize graphs:
http://llvm.org/docs/ProgrammersManual.html#ViewGraph

Once you have that, you can pass -view-legalize-dags, -view-isel-dags, and 
-view-sched-dags to llc to see the dags at various points in time.  To 
debug isel problems, -view-isel-dags should do it.

> I am trying to make the ARM backend compile
>
> int f() {return 0;}
>
> I have added a custom expansion of ret that is similar to the one used
> in ppc and sparc. If I understand it correctly, it will expand the ret
> into an assignment to the return register (R0) and a RETFLAG node.
>
> I declared the bx instruction to match RETFLAG.

Ok.

> Now the instruction selection says it can't match "
> i32 = Constant <0>"
>
> I tried to declare a fake mov that is capable of moving arbitrary i32
> constants to a register (ops IntRegs:$dst, i32imm:$src). But the error
> is still the same.
>
> Does anyone has a suggestion on what the problem might be?

It's most likely that your move doesn't have a pattern.  In particular, in 
addition to specifying the operands, you also need to specify what what 
opcode does.  In this case, a pattern like the X86 MOV32ri instruction is 
probably what you want:

   [(set GR32:$dst, imm:$src)]

Of course, replace GR32/IntRegs as appropriate.

-Chris

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