[LLVMdev] TableGen: RegisterClass question

[Chris Lattner]

On Sat, 13 May 2006, Vladimir Prus wrote:
> I'm porting some existing code of mine to CVS HEAD, and don't understand
> something about new RegisterClass TableGen definition:
>
>    class RegisterClass<string namespace, list<ValueType> regTypes,........
>    {
>       .....
>       string Namespace = namespace;
>
> What is this "namespace" thing? It looks like it should contain the name of
> backend, right?

Right.  This is "X86" "Alpha" "PPC" etc, which is used to prefix register 
names and other things (PPC::R1 for example).  Something short but unique 
is good.

>  // RegType - Specify the ValueType of the registers in this register
>  // class. Note that all registers in a register class must have the same
>  // ValueType.
>  list<ValueType> RegTypes = regTypes;
>
> The comment seems out of date -- it says that only one type is allowed,
> while list is used.

Thanks, fixed!

> Can somebody explain what would it mean for a register
> class to have several allowed ValueTypes?

This is useful for targets where multiple types of the same size can be 
held in the same registers.  For example, if the target has a unified 
register file for Int/FP, it could have [i64, f64].  In practice, this is 
most useful for vector types, the X86 backend has [v16i8, v8i16, v4i32, 
v2i64, v4f32, v2f64].

-Chris

-- 
http://nondot.org/sabre/
http://llvm.org/