[LLVMdev] floating point exception and SSE2 instructions

[Chris Lattner]

On Thu, 20 Apr 2006, Simon Burton wrote:
>>> From what I remember, this is a bug in debian libc:
>> some floating point flags are set incorrectly causing SIGFPE.
>> Can't find the bug report ATM.
>
> Oh, it just showed up on numpy-discussion:
> http://sources.redhat.com/bugzilla/show_bug.cgi?id=10
>
> """
> #include <fenv.h>
> void feclearexcept(int ex)
>
> This function should clear the specified exception status bits in the 
> FPU status register. For CPUs with SSE support it should also clear the 
> MXCSR status register bits.
>
> The problem is that feclearexcept() clears the status control bits also,
> causing future floating-point errors to generate interrupts which will
> lead to a SIGFPE signal which terminates the program (unless caught by a
> SIGFPE handler).
> """

I don't see what this has to do with anything, but...

> Is there a way I can disable SSE instruction generation in LLVM ?

Yes.  Pass -mattr=-sse1,-sse2,-sse3 to lli or llc.

If you've linked the JIT into your app, you can specify this by calling 
cl::ParseCommandLineOptions on an static array, something like:

int argc;
char *Args[] = { "", "-mattr=-sse1,-sse2,-sse3", 0 };
cl::ParseCommandLineOptions(argc, Args, 0);

-Chris

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