[LLVMdev] avoid live range overlap of "vector" registers

[Morten Ofstad]

Chris Lattner wrote:
> On Fri, 6 May 2005, Tzu-Chien Chiu wrote:
> 
>> a "vector" register r0 is composed of four 32-bit floating scalar
>> registers, r0.x, r0.y, r0.z, r0.w.
>>
>> each scalar reg can be assigned individually, e.g.
>>
>>  mov r0.x, r1.y
>>  add r0.y, r1,x, r2.z
>>
>> or assigned simultaneously with vector instructions, e.g.
>>
>>  add r0.xyzw, r1.xzyw, r2.xyzw
>>
>> My question is how to define the register in .td file to avoid the
>> code generator overlaps the live ranges of vector registers?
> 
> If you want to access each part individually, I would suggest doing the 
> tedious thing and including them all.  The IA64 backend has 3*128 
> registers, so there is precedent for this...

Actually, I think it would be better to define the registers as a machine value type for packed float x4, and providing 
some 'extract' and 'inject' instructions to access individual components... There should also be a 'shuffle' instruction 
(corresponding to the SSE PSHUF instruction) to change the individual components around.

m.