[LLVMdev] Making a pass available to llc?

[Michael McCracken]

Attached is my patch that adds a (debug build only) verifier pass and
support for creating passes specified on the command line to llc.

Let me know if it needs changes to be acceptable. One thing I noticed
is that (eg.) opt and analyze have their options and globals in an
anonymous namespace while llc doesn't. I just used llc's convention -
which is preferable?

As to testing - It works as expected with my loadable analysis pass,
but I'm not set up to run llvm-test. I should really get that going.

I didn't add any pass printing code like what opt and analyze have
(under "-p" in opt) because it didn't seem like llc needs to be
printing its passes.

-mike

On 7/26/05, Chris Lattner <sabre at nondot.org> wrote:
> On Tue, 26 Jul 2005, Michael McCracken wrote:
> >> I can't see any harm in that. However, please make sure that it really
> >> isn't being run. The verifier can be hidden by various levels of
> >> abstraction.
> >
> > Assuming that I get everything with -debug-pass=Structure, then it isn't:
> 
> -debug-pass=Structure does list everything.  If you add it, please add it
> in an "#ifndef NDEBUG" block so that it does not penalize the release
> build.
> 
> Thanks!
> 
> -Chris
> 
> > % llc -march=x86 -stats -f tests/IS/npbis.bc -debug-pass=Structure
> > Pass Arguments:  -lowergc -lowerinvoke -lowerswitch -unreachableblockelim
> > Target Data Layout
> > Module Pass Manager
> >  Function Pass Manager
> >    Lower GC intrinsics, for GCless code generators
> > --  Lower GC intrinsics, for GCless code generators
> >    Lower invoke and unwind, for unwindless code generators
> > --  Lower invoke and unwind, for unwindless code generators
> >    Lower SwitchInst's to branches
> > --  Lower SwitchInst's to branches
> >    Remove unreachable blocks from the CFG
> > --  Remove unreachable blocks from the CFG
> >    X86 Pattern Instruction Selection
> > --  X86 Pattern Instruction Selection
> >    Live Variable Analysis
> >    Eliminate PHI nodes for register allocation
> >    Two-Address instruction pass
> >    Immediate Dominators Construction
> >    Dominator Set Construction
> > --  Immediate Dominators Construction
> >    Natural Loop Construction
> > --  Dominator Set Construction
> >    Live Interval Analysis
> > --  Natural Loop Construction
> > --  Live Variable Analysis
> > --  Eliminate PHI nodes for register allocation
> > --  Two-Address instruction pass
> >    Linear Scan Register Allocator
> > --  Live Interval Analysis
> > --  Linear Scan Register Allocator
> >    Live Variable Analysis
> >    X86 FP Stackifier
> > --  Live Variable Analysis
> > --  X86 FP Stackifier
> >    Prolog/Epilog Insertion & Frame Finalization
> > --  Prolog/Epilog Insertion & Frame Finalization
> >    X86 Peephole Optimizer
> > --  X86 Peephole Optimizer
> >    X86 AT&T-Style Assembly Printer
> > --  X86 AT&T-Style Assembly Printer
> >    Machine Code Deleter
> > --  Machine Code Deleter
> >
> >
> > I'll add it. I managed to uncover a bug in my own code with my new
> > version of llc, though, so I might not have a patch to send tonight,
> > but I will soon.
> >
> > Thanks,
> > -mike
> >
> >
> 
> -Chris
> 
> --
> http://nondot.org/sabre/
> http://llvm.org/
> 


-- 
Michael McCracken
UCSD CSE PhD Candidate
research: http://www.cse.ucsd.edu/~mmccrack/
misc: http://michael-mccracken.net/blog/
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